DAC8248

–8–

REV. B

Four Cycle Update

Five Cycle Update

Write Timing Cycle Diagram

PARAMETER DEFINITIONS

RESOLUTION (N)

The resolution of a DAC is the number of states (2

full-scale range (FSR) is divided (or resolved) into; where n is

equal to the number of bits.

RELATIVE ACCURACY (INL)

Relative accuracy, or integral nonlinearity, is the maximum de-

viation of the analog output (from the ideal) from a straight line

drawn between the end points. It is expressed in terms of least

significant bit (LSB), or as a percent of full scale.

DIFFERENTIAL NONLINEARITY (DNL)

Differential nonlinearity is the worst case deviation of any adja-

cent analog output from the ideal 1 LSB step size. The devia-

tion of the actual “step size” from the ideal step size of 1 LSB is

called the differential nonlinearity error or DNL. DACs with

DNL greater than

±1 LSB may be nonmonotonic. ±1/2 LSB

INL guarantees monotonicity and

±1 LSB maximum DNL.

Gain error is the difference between the actual and the ideal

analog output range, expressed as a percent of full-scale or in

terms of LSB value. It is the deviation in slope of the DAC

transfer characteristic from ideal.

Refer to PMI 1990/91 Data Book, Section 11, for additional

digital-to-analog converter definitions.

GENERAL CIRCUIT DESCRIPTION

CONVERTER SECTION

The DAC8248 incorporates two multiplying 12-bit current out-

put CMOS digital-to-analog converters on one monolithic chip.

It contains two highly stable thin-film R-2R resistor ladder net-

works, two 12-bit DAC registers, two 8-bit input registers, and

two 4-bit input registers. It also contains the DAC control logic

circuitry and 24 single-pole, double-throw NMOS transistor

current switches.

Figure 1 shows a simplified circuit for the R-2R ladder and tran-

sistor switches for a single DAC. R is typically 11 k

Ω. The tran-

sistor switches are binarily scaled in size to maintain a constant

voltage drop across each switch. Figure 2 shows a single NMOS

transistor switch.

Figure 1. Simplified Single DAC Circuit Configuration.

(Switches Are Shown For All Digital Inputs at Zero)