AD7664 datasheet(15/28 Pages) AD

15 / 28 page

AD7679

Rev. A | Page 15 of 28

CIRCUIT INFORMATION

IN+

REF

REFGND

IN–

MSB

LSB

SW+

SWITCHES

CONTROL

262,144C 131,072C

MSB

LSB

SW–

BUSY

OUTPUT

CODE

CNVST

CONTROL

LOGIC

COMP

262,144C 131,072C

03085–0–025

Figure 23. ADC Simplified Schematic

The AD7679 is a very fast, low power, single-supply, precise

18-bit analog-to-digital converter (ADC) using successive

approximation architecture.

The AD7679’s linearity and dynamic range are similar or better

than many Σ-Δ ADCs. With the advantages of its successive

architecture, which ease multiplexing and reduce power with

throughput, it can be advantageous in applications that

normally use Σ-Δ ADCs.

The AD7679 provides the user with an on-chip track/hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

The AD7679 can be operated from a single 5 V supply and can

be interfaced to either 5 V or 3 V digital logic. It is housed in a

48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings

and allows for flexible configurations as either a serial or

parallel interface. The AD7679 is pin-to-pin compatible with

the AD7674, AD7676, and AD7678.

CONVERTER OPERATION

The AD7679 is a successive approximation ADC based on a

charge redistribution DAC. Figure 23 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 18 binary weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to AGND via SW+ and SW–.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on IN+ and IN– inputs. When the

acquisition phase is complete and the CNVST input goes low, a

conversion phase is initiated. When the conversion phase

begins, SW+ and SW– are opened first. The two capacitor

arrays are then disconnected from the inputs and connected to

the REFGND input. Therefore, the differential voltage between

the IN+ and IN– inputs captured at the end of the acquisition

phase is applied to the comparator inputs, causing the

comparator to become unbalanced. By switching each element

of the capacitor array between REFGND and REF, the

comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4...VREF/262144). The control logic toggles these

switches, starting with the MSB first, to bring the comparator

back into a balanced condition. After completing this process,

the control logic generates the ADC output code and brings the

BUSY output low.

AD7664 датащи(PDF) 15 Page - Analog Devices

AD7664 датащи(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL