AD5325ARM datasheet(15/24 Pages) AD

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AD5305/AD5315/AD5325

Rev. G | Page 15 of 24

FUNCTIONAL DESCRIPTION

The AD5305/AD5315/AD5325 are quad resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and 12

bits, respectively. Each contains four output buffer amplifiers

and is written to via a 2-wire serial interface. They operate from

single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers

provide rail-to-rail output swing with a slew rate of 0.7 V/μs.

The four DACs share a single reference input pin. The devices

have three programmable power-down modes, in which all

DACs can be turned off completely with a high impedance

output, or the outputs can be pulled low by on-chip resistors.

DIGITAL-TO-ANALOG SECTION

The architecture of one DAC channel consists of a resistor-

string DAC followed by an output buffer amplifier. The voltage

at the REFIN pin provides the reference voltage for the DAC.

Figure 29 shows a block diagram of the DAC architecture.

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by

REF

OUT

where:

D = decimal equivalent of the binary code, which is loaded to

the DAC register:

0 to 255 for AD5305 (8 bits)

0 to 1023 for AD5315 (10 bits)

0 to 4095 for AD5325 (12 bits)

N = DAC resolution

REFIN

INPUT

DAC

RESISTOR

STRING

OUTPUT BUFFER

AMPLIFIER

VOUTA

Figure 29. DAC Channel Architecture

RESISTOR STRING

The resistor string section is shown in Figure 30. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at what node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

TO OUTPUT

AMPLIFIER

Figure 30. Resistor String

DAC REFERENCE INPUTS

There is a single reference input pin for the four DACs. The

reference input is unbuffered. The user can have a reference

voltage as low as 0.25 V and as high as VDD because there is no

restriction due to headroom and footroom of any reference

amplifier.

It is recommended to use a buffered reference in the external

circuit (for example, REF192). The input impedance is typically

45 kΩ.

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, which gives an output range of 0 V to

VDD when the reference is VDD. It is capable of driving a load of

2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD.

The source and sink capabilities of the output amplifier can be

seen in the plot in Figure 14.

The slew rate is 0.7 V/μs with a half-scale settling time to

±0.5 LSB (at eight bits) of 6 μs.

POWER-ON RESET

The AD5305/AD5315/AD5325 are provided with a power-on

reset function, so that they power up in a defined state. The

power-on state is

•

Normal operation

•

Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain

so until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

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