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SLAS191A датащи(PDF) 37 Page - Texas Instruments

номер детали SLAS191A
подробное описание детали  Starter Kit Evaluation Kit Manual
PDF  86 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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SLAS191A датащи(HTML) 37 Page - Texas Instruments

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2–1
2 Monitor Commands
This chapter describes the syntax conventions and the available commands of the Monitor Program.
2.1
Syntax Conventions
The numbers in brackets [ ] are optional.
x is a hexadecimal address.
n is the hexadecimal number of bytes to show.
i is the hexadecimal register number.
Only the r, m, and e commands expect <ENTER> or <ESC> commands.
The <ESC> key provides a keyboard interrupt for all command inputs except m.
The half-duplex UART prevents keyboard interrupts while entering a large number of bytes to
show the results of an action.
The registers are named in hexadecimal format from R0 to RF.
All addresses or memory/register contents must be entered in hexadecimal mode. Entering
zeros in the MSB is optional.
Errors in address or memory/register contents in the terminal input must be corrected by
re-entering all four hexadecimal digits. The leading (MSB) zeros are optional.
The Arrow, Insert, Delete, or Backspace keys can not be used to change an incorrect terminal
input.
2.2
Memory Organization
To use some commands, it is necessary to know the memory locations and their functions (see Figure 2–1).
In memory locations 000h to 0FFh, only the byte mode is possible. In memory locations 100h to 1FFh, only
the word mode is possible. Memory locations 010h to 0FFh are reserved for 8-bit peripheral modules, and
the locations between 100h and 1FFh are reserved for 16-bit peripheral modules.
INT. VECTOR
16 KB EPROM
512 B RAM
16 Bit Peripheral Modules
8 Bit Peripheral Modules
Special Function Register
FFFFh
FFE0h
FFDFh
C000h
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
INT. VECTOR
32 KB EPROM
1 KB RAM
16 Bit Peripheral Modules
8 Bit Peripheral Modules
Special Function Register
FFFFh
FFE0h
FFDFh
8000h
05FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430x320
MSP430x330
Figure 2–1. Memory Organization



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