EP3C5 datasheet(41/274 Pages) ALTERA

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Chapter 3: Memory Blocks in the Cyclone III Device Family

3–7

Memory Modes

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Asynchronous Clear

The Cyclone III device family supports asynchronous clears for read address registers,

output registers, and output latches only. Input registers other than read address

registers are not supported. When applied to output registers, the asynchronous clear

signal clears the output registers and the effects are immediately seen. If your RAM

does not use output registers, you can still clear the RAM outputs using the output

latch asynchronous clear feature.

1 Asserting asynchronous clear to the read address register during a read operation

might corrupt the memory content.

Figure 3–6 shows the functional waveform for the asynchronous clear feature.

1 You can selectively enable asynchronous clears per logical memory using the

Quartus II RAM MegaWizard™ Plug-In Manager.

f For more information, refer to the Internal Memory (RAM and ROM) User Guide.

There are three ways to reset registers in the M9K blocks:

■

Power up the device

■

Use the aclr signal for output register only

■

Assert the device-wide reset signal using the DEV_CLRn option

Memory Modes

Cyclone III device family M9K memory blocks allow you to implement

fully-synchronous SRAM memory in multiple modes of operation. Cyclone III device

family M9K memory blocks do not support asynchronous (unregistered) memory

inputs.

M9K memory blocks support the following modes:

■

Single-port

■

Simple dual-port

■

True dual-port

■

Shift-register

■

ROM

■

FIFO

Figure 3–6. Output Latch Asynchronous Clear Waveform

aclr

aclr at latch

clk

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