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PPC5604EEMLH датащи(PDF) 55 Page - Freescale Semiconductor, Inc |
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PPC5604EEMLH датащи(HTML) 55 Page - Freescale Semiconductor, Inc |
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55 / 75 page ![]() Electrical characteristics MPC5604E Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 55 3.18.8 DSPI timing Table 32. DSPI timing No. Symbol C Parameter Conditions Min Max Unit 1tSCK CC D DSPI cycle time Master (MTFE = 0) 62.5 — ns Slave (MTFE = 0) 128 — Master (MTFE = 1,CPHA=1) 31.25 — 2tCSC CC D CS to SCK delay — 16 — ns 3tASC CC D After SCK delay — 16 — ns 4tSDC CC D SCK duty cycle — 0.4 * tSCK 0.6 * tSCK ns 5tA CC D Slave access time SS active to SOUT valid — 40 ns 6tDIS CC D Slave SOUT disable time SS inactive to SOUT High-Z or invalid — 10 ns 7tPCSC CC D PCSx to PCSS time — 13 — ns 8tPASC CC D PCSS to PCSx time — 13 — ns 9tSUI CC D Data setup time for inputs Master (MTFE = 0) 12 — ns Slave 2— Master (MTFE = 1, CPHA = 0) NA1 1 This mode is not feasible at 32 MHz. Master (MTFE = 1, CPHA = 1) 12 — 10 tHI CC D Data hold time for inputs Master (MTFE = 0) –5 — ns Slave 4 — Master (MTFE = 1, CPHA = 0) NA1 Master (MTFE = 1, CPHA = 1) –5 — 11 tSUO CC D Data valid (after SCK edge) Master (MTFE = 0) — 4 ns Slave — 33 Master (MTFE = 1, CPHA = 0) NA1 Master (MTFE = 1, CPHA = 1) — 11 12 tHO CC D Data hold time for outputs Master (MTFE = 0) –2 — ns Slave 6 — Master (MTFE = 1, CPHA = 0) NA1 Master (MTFE = 1, CPHA = 1) –2 — |
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