Rev. 1.0 / Sep. 2012

3

Description

The H5TC2G83DFR-xxA(I) and H5TC2G63DFR-xxA(I) are a 2Gb low power Double Data Rate III (DDR3L)

Synchronous DRAM, ideally suited for the main memory applications which requires large memory density,

high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibil-

ity with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for

details.)

SK Hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling

edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (fall-

ing edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and

falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-

width.

Device Features and Ordering Information

FEATURES

* This product in compliance with the RoHS directive.

• VDD=VDDQ=1.35V + 0.100 / - 0.067V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On chip DLL align DQ, DQS and DQS transition with CK

transition

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and

13

supported

• Programmable additive latency 0, CL-1, and CL-2

supported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

• BL switch on the fly

• 8banks

• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• 8 bit pre-fetch