EMC1413 datasheet(30/52 Pages) SMSC

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Multiple Channel 1°C Temperature Sensors with Beta Compensation

Datasheet

Revision 1.41 (02-23-12)

SMSC EMC1413 / EMC1414

DATASHEET

7.3

Status Register

The Status Register reports general error conditions. To identify specific channels, refer to

Section 7.10, Section 7.15, Section 7.16, and Section 7.17. The individual Status Register bits are

cleared when the appropriate High Limit, Low Limit, or Therm Limit register has been read or cleared.

Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either

the ALERT or THERM pins to be asserted.

Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.

See the High Limit Status Register for specific channel information (Section 7.15). When set, this bit

will assert the ALERT pin.

Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low

limit. See the Low Limit Status Register for specific channel information (Section 7.16). When set, this

bit will assert the ALERT pin.

Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode

channels. See the External Diode Fault Register for specific channel information (Section 7.10). When

set, this bit will assert the ALERT pin.

Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed

Therm Limit. See the Therm Limit Status Register for specific channel information (Section 7.17).

7.4

Configuration Register

The Configuration Register controls the basic operation of the device. This register is fully accessible

at either address.

Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.

‘0’ - (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT

pin will be asserted.

‘1’ - - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is

configured in comparator mode. The Status Registers will be updated normally.

Bit 6 - RUN / STOP - Controls Active/Standby modes.

‘0’ (default) - The device is in Active mode and converting on all channels.

‘1’ - The device is in Standby mode and not converting.

Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.

‘0’ (default) - The ALERT pin acts as described in Section 6.3.

‘1’ - The ALERT pin acts in comparator mode as described in Section 6.3.2. In this mode the

MASK_ALL bit is ignored.

Table 7.3 Status Register

ADDR

R/W

DEFAULT

02h

Status

BUSY

HIGH

LOW

FAULT

THERM

00h

Table 7.4 Configuration Register

ADDR

R/W

DEFAULT

03h

R/W

Configuration

MASK_

ALL

RUN/

STOP

ALERT/

COMP

RECD1

RECD2

RANGE

DAVG_

DIS

APDD

00h

09h

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