H5TQ2G43CFR-RDC datasheet(28/33 Pages) HYNIX

номер детали	H5TQ2G43CFR-RDC

подробное описание детали	2Gb DDR3 SDRAM

PDF	33 Pages

Scroll/Zoom	100%

производитель	HYNIX [Hynix Semiconductor]

домашняя страница	http://www.skhynix.com/kor/main.do

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28 / 33 page

Rev. 1.0 / Apr. 2013

DDR3-1333 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 32.

Speed Bin

DDR3-1333H

Unit

Note

CL - nRCD - nRP

9-9-9

Parameter

Symbol

min

max

Internal read

command to first data

tAA

13.5

(13.125)5,11

ACT to internal read or

write delay time

tRCD

13.5

(13.125)5,11

—ns

PRE command period

tRP

13.5

(13.125)5,11

—ns

ACT to ACT or REF

command period

tRC

49.5

(49.125)5,11

—ns

ACT to PRE command

period

tRAS

9 * tREFI

CL = 5

CWL = 5

tCK(AVG)

3.0

3.3

1,2,3,4,7,12,13

CWL = 6, 7 tCK(AVG)

Reserved

CL = 6

CWL = 5

tCK(AVG)

2.5

3.3

1,2,3,7

CWL = 6

tCK(AVG)

Reserved

1,2,3,4,7

CWL = 7

tCK(AVG)

Reserved

CL = 7

CWL = 5

tCK(AVG)

Reserved

CWL = 6

tCK(AVG)

1.875

< 2.5

1,2,3,4,7

(Optional)5,11

CWL = 7

tCK(AVG)

Reserved

1,2,3,4

CL = 8

CWL = 5

tCK(AVG)

Reserved

CWL = 6

tCK(AVG)

1.875

< 2.5

1,2,3,7

CWL = 7

tCK(AVG)

Reserved

1,2,3,4

CL = 9

CWL = 5, 6 tCK(AVG)

Reserved

CWL = 7

tCK(AVG)

1.5

<1.875

1,2,3,4

CL = 10

CWL = 5, 6 tCK(AVG)

Reserved

CWL = 7

tCK(AVG)

1.5

<1.875

1,2,3

(Optional)

Supported CL Settings

5, 6, 7, 8, 9, 10

nCK

Supported CWL Settings

5, 6, 7

nCK

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