MIC4604 datasheet(15/18 Pages) MICREL

15 / 18 page

Micrel, Inc.

MIC4604

June 25, 2013

Revision 1.0

Figure 13. Type I Inverter Topology

As shown in Figure 13, Type I is a dual-stage topology

where line

voltage is converted to DC through a

transformer to charge the storage batteries. When a power

failure is detected, the stored DC energy is converted to

AC through another transformer to drive the AC loads

connected to the inverter output. This method is simplest

to design but tends to be bulky and expensive because it

uses two transformers.

Type II is a single-stage topology that uses only one

transformer to charge the bank of batteries to store the

energy. During a power outage, the same transformer is

used to power the line voltage. The Type II switches at a

higher frequency compared to the Type I topology to

maintain a small transformer size.

Both types require a half bridge or full bridge topology to

boost the DC to AC. This application can use two

MIC4604s. The 85V operating voltage offers enough

margin to address all of the available banks of batteries

commonly used in inverter applications. The 85V operating

voltage allows designers to increase the bank of batteries

up to 72V, if desired. The MIC4604 can sink as much as

1A, which is enough current to overcome the MOSFET’s

input capacitance and switch the MOSFET up to 50kHz.

This makes the MIC4604 an ideal solution for inverter

applications.

As with all half bridge and full bridge topologies, cross

conduction is a concern to inverter manufactures because

it can cause catastrophic failure. This can be remedied by

adding the appropriate dead time between transitioning

from the high-side MOSFET to the low-side MOSFET and

vice versa.

Layout Guidelines

Use the following layout guidelines for optimum circuit

performance:

•

Place the VDD and HB bypass capacitors close to the

supply and ground pins. It is critical that the etch

length between the high side decoupling capacitor (CB)

and the HB and HS pins be minimized to reduce lead

inductance.

•

Use a ground plane to minimize parasitic inductance

and impedance of the return paths. The MIC4604 is

capable of greater than 1A peak currents and any

impedance between the MIC4604, the decoupling

capacitors, and the external MOSFET will degrade the

performance of the driver.

•

Trace out the high di/dt and dv/dt paths, as shown in

Figure 14 and Figure 15, and minimize etch length and

loop area for these connections. Minimizing these

parameters decreases the parasitic inductance and

the radiated EMI generated by fast rise and fall times.

A typical layout of a synchronous Buck converter power

stage (Figure 14) is shown in Figure 15 .

Figure 14. Synchronous Buck Converter Power Stage

The high-side MOSFET drain connects to the input supply

voltage (drain) and the source connects to the switching

node. The low-side MOSFET drain connects to the

switching node and its source is connected to ground. The

buck converter output inductor (not shown) connects to the

switching node. The high-side drive trace, HO, is routed on

top of its return trace, HS, to minimize loop area and

parasitic inductance. The low-side drive trace LO is routed

over the ground plane to minimize the impedance of that

current path. The decoupling capacitors, CB and CVDD, are

placed to minimize etch length between the capacitors and

their respective pins. This close placement is necessary to

efficiently charge capacitor CB when the HS node is low.

All

traces

are

0.025in

wide

greater

reduce

impedance. CIN is used to decouple the high current path

through the MOSFETs.

MIC4604 датащи(PDF) 15 Page - Micrel Semiconductor

MIC4604 датащи(HTML) 15 Page - Micrel Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

датащи скачать

ссылки URL