CN-0046

Circuit Note

Rev. A | Page 2 of 3

AD8352

24.9

Ω

64.9

Ω

50

Ω

0.1µF

0.1µF

AC

VIP

5V

VIN

200

Ω

33

Ω

33

Ω

0.1µF

0.1µF

0.1µF

VOP

VON

AD9445

VIN+

VIN–

Figure 2. Single-Ended Input to the AD8352 Driving the AD9445 ADC

(Simplified Schematic, All Connections Not Shown)

differential FFT plots in Figure 3 and Figure 4. The single-

ended circuit avoids the use of a transformer or balun in

front of the amplifier while still maintaining excellent

distortion up to approximately 100 MHz. However, at

frequencies above approximately 100 MHz, second-order

distortion increases when the AD8352 is driven single-ended

due to phase-related errors.

0

–150

0

52.50

FREQUENCY (MHz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25

SNR = 67.26dBc

SFDR = 83.18dBc

NOISE FLOOR = –110.5dB

FUND = –1.074dBFS

SECOND = –83.14dBc

THIRD = –85.39dBc

Figure3.SingleToneDistortion,AD8352DrivingAD9445,SamplingClock=105MSPS,

distortion cancellation. The AD9445 differential input

impedance is approximately 2 kΩ in parallel with 5 pF and

The output of the amplifier is ac-coupled to allow for an

optimum common-mode voltage at the ADC input. The

common-mode voltage at the input of the AD9445 is set to

3.5 V by an internal network. Input ac-coupling can be

required if the source also requires a common-mode voltage

common-mode pin is provided on the AD8352 that equally

shifts both input and output common-mode levels. Increasing

the gain of the AD8352 increases the system noise and, thus,

the AD9445 when no filtering is used. However, it should be

noted that amplifier gains from 3 dB to 18 dB, with proper

levels. These circuits, when configured properly, can result in

SFDR performance of better than 87 dBc at 70 MHz and 82 dBc

levels as shown in these figures.

Excellent layout, grounding, and decoupling techniques must be

utilized in order to achieve the desired performance from the

circuits discussed in this note. As a minimum, a 4-layer PCB

should be used with one ground plane layer, one power plane

layer, and two signal layers.

All IC power pins must be decoupled to the ground plane

with low inductance multilayer ceramic capacitors (MLCC)

of 0.01 µF to 0.1 µF (this is not shown in the diagrams for

simplicity). Follow the recommendations on the individual

data sheets for the ICs.

The product evaluation boards should be consulted for

recommended layout and critical component placement. They

can be accessed through the main product pages for the devices

or their data sheets.

FREQUENCY (MHz)

0

–150

0

52.50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25

SNR = 61.98dBc

NOISE FLOOR = –111.2dB

FUND1 = –7.072dBFS

FUND2 = –7.043dBFS

IMD (2F2-F1) = –89dBc

IMD (2F1-F2) = –88dBc

Figure 4. Two Tone Intermodulation Distortion, AD8352 Driving AD9445,

Sampling Clock = 105 MSPS, Analog Input Frequency = 98 MHz and