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Rev. A | Page 5 of 16

TIMING SPECIFICATIONS

Table 5.

Parameter

Symbol

Min

Typ

Max

Unit

Throughput Rate

100

kHz

CS Falling to DCLOCK Low

0

μs

CS Falling to DCLOCK Rising

20

ns

DCLOCK Falling to Data Remains Valid

5

16

ns

14

100

ns

DCLOCK Falling to Data Valid

16

50

ns

Acquisition Time

400

ns

11

25

ns

11

25

ns

Timing Diagrams

DCLOCK

COMPLETE CYCLE

POWER DOWN

CS

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

(MSB)

(LSB)

Hi-Z

0

Hi-Z

0

14

5

NOTE:

A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.

Figure 2. Serial Interface Timing

500

μAI

OL

500

μAI

OH

1.4V

100pF

Figure 3. Load Circuit for Digital Interface Timing

0.8V

2V

2V

0.8V

0.8V

2V

Figure 4. Voltage Reference Levels for Timing

90%

10%