AD9854AST datasheet(37/52 Pages) AD

37 / 52 page

AD9854

Rev. E | Page 37 of 52

INSTRUCTION BYTE

The instruction byte contains the following information:

MSB

LSB

R/W

R/W—Bit 7 determines whether a read or write data transfer

occurs following the instruction byte. Logic high indicates read

operation. Logic 0 indicates a write operation.

Bit 6, Bit 5, and Bit 4 are dummy bits (don’t care).

A3, A2, A1, A0—Bit 3, Bit 2, Bit 1, and Bit 0 determine which

communication cycle (see Table 8 for register address details).

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK

Serial Clock (Pin 21). The serial clock pin is used to synchronize

data to and from the AD9854 and to run the internal state

machines. The SCLK maximum frequency is 10 MHz.

Chip Select (Pin 22). Active low input that allows more than

one device on the same serial communication line. The SDO

and SDIO pins go to a high impedance state when this input is

high. If this pin is driven high during a communication cycle,

the cycle is suspended until CS is reactivated low. The chip select

pin can be tied low in systems that maintain control of SCLK.

SDIO

Serial Data I/O (Pin 19). Data is always written to the AD9854

on this pin. However, this pin can be used as a bidirectional

data line. The configuration of this pin is controlled by Bit 0 of

configures the SDIO pin as bidirectional.

SDO

Serial Data Out (Pin 18). Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In

the case where the AD9854 operates in a single bidirectional

I/O mode, this pin does not output data and is set to a high

impedance state.

IO RESET

Synchronize I/O Port (Pin 17). Synchronizes the I/O port state

machines without affecting the contents of the addressable

registers. An active high input on the IO RESET pin causes the

current communication cycle to terminate. After the IO RESET

pin returns low (Logic 0), another communication cycle can begin,

starting with the instruction byte.

NOTES ON SERIAL PORT OPERATION

The AD9854 serial port configuration bits reside in Bit 1 and

Bit 0 of Register Address 20 hex. It is important to note that the

configuration changes immediately upon a valid I/O update.

For multibyte transfers, writing to this register can occur during

the middle of a communication cycle. The user must compensate

for this new configuration for the remainder of the current com-

munication cycle.

The system must maintain synchronization with the AD9854;

otherwise, the internal control logic is not able to recognize further

instructions. For example, if the system sends the instruction to

write a 2-byte register and then pulses the SCLK pin for a 3-byte

synchronization is lost. In this case, the first 16 SCLK rising

edges after the instruction cycle properly write the first two data

bytes into the AD9854, but the subsequent eight rising SCLK

edges are interpreted as the next instruction byte, not the final

byte of the previous communication cycle.

In the case where synchronization is lost between the system

and the AD9854, the IO RESET pin provides a means to re-

establish synchronization without reinitializing the entire chip.

Asserting the IO RESET pin (active high) resets the AD9854 serial

port state machine, terminating the current I/O operation and

forcing the device into a state in which the next eight SCLK rising

edges are understood to be an instruction byte. The IO RESET pin

must be deasserted (low) before the next instruction byte write

can begin. Any information written to the AD9854 registers

during a valid communication cycle prior to loss of synchroni-

zation remains intact.

SCLK

SDIO

tPRE

tDSU tSCLKPWH tSCLKPWL

tSCLK

tDHLD

SECOND BIT

FIRST BIT

SYMBOL

MIN

DEFINITION

CS SETUP TIME

PERIOD OF SERIAL DATA CLOCK

SERIAL DATA SETUP TIME

SERIAL DATA CLOCK PULSE WIDTH HIGH

SERIAL DATA CLOCK PULSE WIDTH LOW

SERIAL DATA HOLD TIME

tPRE

tSCLK

tDSU

tSCLKPWH

tSCLKPWL

tDHLD

30ns

100ns

30ns

40ns

0ns

Figure 56. Timing Diagram for Data Write to AD9854

INSTRUCTION

CYCLE

DATA TRANSFER

INSTRUCTION

BYTE

SDIO

DATA TRANSFER

DATA BYTE 1

DATA BYTE 2

DATA BYTE 3

SDO

Figure 57. Timing Diagram for Read from AD9854

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