FLEX10KA datasheet(15/128 Pages) ALTERA

15 / 128 page

Altera Corporation

FLEX 10K Embedded Programmable Logic Device Family Data Sheet

The programmable flipflop in the LE can be configured for D, T, JK, or SR

operation. The clock, clear, and preset control signals on the flipflop can

be driven by global signals, general-purpose I/O pins, or any internal

logic. For combinatorial functions, the flipflop is bypassed and the output

of the LUT drives the output of the LE.

The LE has two outputs that drive the interconnect; one drives the local

interconnect and the other drives either the row or column FastTrack

Interconnect. The two outputs can be controlled independently. For

example, the LUT can drive one output while the register drives the other

output. This feature, called register packing, can improve LE utilization

because the register and the LUT can be used for unrelated functions.

The FLEX 10K architecture provides two types of dedicated high-speed

data paths that connect adjacent LEs without using local interconnect

paths: carry chains and cascade chains. The carry chain supports high-

speed counters and adders; the cascade chain implements wide-input

functions with minimum delay. Carry and cascade chains connect all LEs

in an LAB and all LABs in the same row. Intensive use of carry and

cascade chains can reduce routing flexibility. Therefore, the use of these

chains should be limited to speed-critical portions of a design.

Carry Chain

The carry chain provides a very fast (as low as 0.2 ns) carry-forward

function between LEs. The carry-in signal from a lower-order bit drives

forward into the higher-order bit via the carry chain, and feeds into both

the LUT and the next portion of the carry chain. This feature allows the

FLEX 10K architecture to implement high-speed counters, adders, and

comparators of arbitrary width efficiently. Carry chain logic can be

created automatically by the Compiler during design processing, or

manually by the designer during design entry. Parameterized functions

such as LPM and DesignWare functions automatically take advantage of

carry chains.

Carry chains longer than eight LEs are automatically implemented by

linking LABs together. For enhanced fitting, a long carry chain skips

alternate LABs in a row. A carry chain longer than one LAB skips either

from even-numbered LAB to even-numbered LAB, or from odd-

numbered LAB to odd-numbered LAB. For example, the last LE of the

first LAB in a row carries to the first LE of the third LAB in the row. The

carry chain does not cross the EAB at the middle of the row. For instance,

in the EPF10K50 device, the carry chain stops at the eighteenth LAB and a

new one begins at the nineteenth LAB.

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