L6566BH datasheet(35/51 Pages) STMICROELECTRONICS

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L6566BH

Application information

Doc ID 16610 Rev 2

35/51

Figure 23.

OVP function: timing diagram

The value of RZ1 is such that the current sourced by the ZCD pin be within the rated

capability of the internal clamp:

Equation 14

where Vinmax is the maximum DC input voltage and Ns the turn number of the primary

winding. See

Section 5.2: Zero-current detection and triggering block; oscillator block for

additional details.

To reduce sensitivity to noise and prevent the latch from being erroneously activated, firstly

the OVP comparator is active only for a small time frame (typically, 0.5 µs) starting 2 µs after

MOSFET turn-off, to reject the voltage spike associated to the positive-going edges of the

voltage across the auxiliary winding Vaux; secondly, to stop the L6566BH, the OVP

comparator must be triggered for four consecutive switching cycles. A counter, which is

reset every time the OVP comparator is not triggered in one switching cycle, is provided for

this purpose.

Figure 22 shows the internal block diagram, while the timing diagrams in Figure 23 illustrate

the operation.

Note:

To use the OVP function effectively, i.e. to ensure that the OVP comparator is always

interrogated during MOSFET OFF-time, the duty cycle D under open loop conditions must

fulfill the following inequality:

AM11499v1

(pin 4)

Vaux

STROBE

COUNTER

RESET

COUNTER

STATUS

ZCD

(pin 11)

2 µs

0.5 µs

OVP

FAULT

COUT

max

Vin

Naux

−

⋅

≥

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