OP196 datasheet(52/88 Pages) AD

52 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 52 of 88

POWER SUPPLY MONITOR

As its name suggests, the power supply monitor, once enabled,

monitors the DVDD supply on the ADuC841/ADuC842/

ADuC843. It indicates when any of the supply pins drops below

one of two user selectable voltage trip points, 2.93 V and 3.08 V.

For correct operation of the power supply monitor function,

AVDD must be equal to or greater than 2.7 V. Monitor function is

controlled via the PSMCON SFR. If enabled via the IEIP2 SFR,

the monitor interrupts the core using the PSMI bit in the

PSMCON SFR. This bit is not cleared until the failing power

supply has returned above the trip point for at least 250 ms.

This monitor function allows the user to save working registers

to avoid possible data loss due to the low supply condition, and

also ensures that normal code execution does not resume until a

safe supply level has been well established. The supply monitor

is also protected against spurious glitches triggering the

interrupt circuit.

Note that the 5 V part has an internal POR trip level of 4.5 V,

which means that there are no usable PSM levels on the 5 V

part. The 3 V part has a POR trip level of 2.45 V, allowing all

PSM trip points to be used.

PSMCON

Power Supply Monitor

Control Register

SFR Address

DFH

Power-On Default

DEH

Bit Addressable

Table 22. PSMCON SFR Bit Designations

Bit No.

Name

Description

----

Reserved.

CMPD

DVDD Comparator Bit.

This is a read-only bit that directly reflects the state of the DVDD comparator.

Read 1 indicates that the DVDD supply is above its selected trip point.

Read 0 indicates that the DVDD supply is below its selected trip point.

PSMI

Power Supply Monitor Interrupt Bit.

This bit is set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The

PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms

counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user.

However, if either comparator output is low, it is not possible for the user to clear PSMI.

TPD1

DVDD Trip Point Selection Bits.

These bits select the DVDD trip point voltage as follows:

TPD1

TPD0

Selected DVDD Trip Point (V)

Reserved

3.08

2.93

TPD0

Reserved

----

Reserved.

----

Reserved.

PSMEN

Power Supply Monitor Enable Bit.

Set to 1 by the user to enable the power supply monitor circuit.

Cleared to 0 by the user to disable the power supply monitor circuit.

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