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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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33FJ64GP710 датащи(PDF) 23 Page - Microchip Technology |
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33FJ64GP710 датащи(HTML) 23 Page - Microchip Technology |
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23 / 90 page  © 2005 Microchip Technology Inc. Preliminary DS70155C-page 21 dsPIC33F 6.5 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. The application program then can either attempt to restart the oscillator, or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. 6.6 Reset System The Reset system combines all Reset sources and controls the device Master Reset signal. Device Reset sources include: • POR: Power-on Reset • BOR: Brown-out Reset •SWR: RESET Instruction • EXTR: MCLR Reset • WDTR: Watchdog Timer Time-out Reset • TRAPR: Trap Conflict • IOPUWR: Attempted execution of an Illegal Opcode, or Indirect Addressing, using an Uninitialized W register |
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