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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD5304ARMZ датащи(PDF) 5 Page - Analog Devices |
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AD5304ARMZ датащи(HTML) 5 Page - Analog Devices |
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5 / 24 page  Data Sheet AD5304/AD5314/AD5324 Rev. H | Page 5 of 24 TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 Limit at TMIN, TMAX VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Test Conditions/Comments t1 40 33 ns min SCLK cycle time t2 16 13 ns min SCLK high time t3 16 13 ns min SCLK low time t4 16 13 ns min SYNC to SCLK falling edge setup time t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min SCLK falling edge to SYNC rising edge t8 80 33 ns min Minimum SYNC high time 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. SCLK DIN DB15 DB0 t1 t3 t2 t7 t5 t4 t6 t8 SYNC Figure 2. Serial Interface Timing Diagram |
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