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AD9914

Data Sheet

Rev. C | Page 2 of 48

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Absolute Maximum Ratings............................................................ 8

Thermal Performance.................................................................. 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 12

Equivalent Circuits......................................................................... 16

Theory of Operation ...................................................................... 17

Single Tone Mode....................................................................... 17

Profile Modulation Mode.......................................................... 17

Digital Ramp Modulation Mode .............................................. 17

Parallel Data Port Modulation Mode....................................... 17

Programmable Modulus Mode................................................. 17

Mode Priority.............................................................................. 18

Functional Block Detail ................................................................. 19

DDS Core .................................................................................... 19

12-Bit DAC Output.................................................................... 20

DAC Calibration Output........................................................... 20

Reconstruction Filter ................................................................. 20

Clock Input (REF_CLK/REF_CLK)........................................ 21

PLL Lock Indication .................................................................. 22

Output Shift Keying (OSK)....................................................... 22

Digital Ramp Generator (DRG)............................................... 23

Power-Down Control ................................................................ 27

Programming and Function Pins................................................. 28

Serial Programming ....................................................................... 31

Control Interface—Serial I/O................................................... 31

General Serial I/O Operation ................................................... 31

Instruction Byte.......................................................................... 31

Serial I/O Port Pin Descriptions .............................................. 31

Serial I/O Timing Diagrams ..................................................... 32

MSB/LSB Transfers .................................................................... 32

Parallel Programming (8-/16-Bit)................................................ 33

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 45

REVISION HISTORY

11/13—Rev. B to Rev. C

Changes to Table 2.............................................................................5

Change to Programming and Function Pins Section.................30

7/13—Rev. A to Rev. B

Change to CMOS Logic Outputs Parameter, Table 1 ...................4

Changes to Table 2.............................................................................7

Changes to DDS Core Section.......................................................19

Changes to Phase-Locked Loop (PLL) Multiplier Section ........21

Changed PLL Charge Pump Section to PLL Charge Pump/

Total Feedback Divider Section; Changes to Table 8, PLL

Loop Filter Components Section, and Figure 34 ........................22

Change to Table 14 ..........................................................................34

Changes to Bits [15:8], Table 17.....................................................42

8/12—Rev. 0 to Rev. A

Changes to Features Section ............................................................1

Changed Differential Input Voltage Unit from mV p-p to V p-p .... 4

Changes to Table 14 ....................................................................... 34

Changes to Table 16 ....................................................................... 40

Changes to Table 28 ....................................................................... 44

Updated Outline Dimensions....................................................... 45

7/12—Revision 0: Initial Version

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