1

MRF255 PHOTOMASTER

MOTOROLA RF DEVICE DATA

The RF MOSFET Line

RF Power

Field-Effect Transistor

N–Channel Enhancement–Mode

Figure 1. 54 MHz Linear RF Test Circuit Electrical Schematic

C1 — 470 pF, Chip Capacitor

C2, C3, C11, C12 — 20 – 200 pF, Trimmer, ARCO #464

C4 — 100 pF, Chip Capacitor

C5, C17 — 100

µF, 15 V, Electrolytic

C6 — 0.001

µF, Disc Ceramic

C7, C8, C9, C10 — 330 pF, Chip Capacitor

C14 — 1200 pF, ATC Chip Capacitor

C15 — 910 pF, 500 V, Dipped Mica

C16 — 47

µF, 16 V, Electrolytic

L1 — 8 Turns, #20 AWG, 0.126

″ ID

L2 — 5 Turns, #18 AWG, 0.142

″ ID

L3 — 3 Turns, #20 AWG, 0.102

″ ID

L4 — 7 Turns, #24 AWG, 0.070

″ ID

L5 — 6.5 Turns, #18 AWG, 0.230

″ ID, 0.5″ Long

N1, N2 — Type N Flange Mount

RFC1 — Ferroxcube VK–200–19/4B

R1 — 39 k

Ω, 1/4 W Carbon

R2 — 150

Ω, 1/4 W Carbon

Board — G–10 .060

″

VGG

VDD

RF

OUTPUT

RF

INPUT

RFC1

+

++

C5

C6

C15

C16

C17

C4

C7

C8

L5

L1

L2

R2

R1

C2

C3

C1

N1

N2

C14

C9

C10

C11

C12

L3

L4

DUT

Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling

and packaging MOS devices should be observed.

Order this document

by MRF255PHT/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MRF255

PHOTOMASTER

CASE 211–11, STYLE 2

REV 1