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2. Operational Description

2.3 Reset Circuit

TMP86FS49FG

2.3 Reset Circuit

The TMP86FS49FG have four types of reset generation procedures: An external reset input, an address trap reset,

a watchdog timer reset and a system clock reset. Table 2-2 shows on-chip hardware initialization by reset action.

The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-

µs at 16.0 MHz) when

power is turned on.

2.3.1 External Reset Input

age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-

ized.

vector address stored at addresses FFFEH to FFFFH.

Figure 2-15 Reset Circuit

Table 2-2 Initializing Internal Status by Reset Action

On-chip Hardware

Initial Value

On-chip Hardware

Initial Value

Program counter

(PC)

(FFFEH)

Prescaler and divider of timing generator

0

Stack pointer

(SP)

Not initialized

General-purpose registers

(W, A, B, C, D, E, H, L, IX, IY)

Not initialized

Jump status flag

(JF)

Not initialized

Watchdog timer

Enable

Zero flag

(ZF)

Not initialized

Output latches of I/O ports

Refer to I/O port circuitry

Carry flag

(CF)

Not initialized

Half carry flag

(HF)

Not initialized

Sign flag

(SF)

Not initialized

Overflow flag

(VF)

Not initialized

Interrupt master enable flag

(IMF)

0

Interrupt individual enable flags

(EF)

0

Control registers

Refer to each of control

register

Interrupt latches

(IL)

0

RAM

Not initialized

Internal reset

RESET

VDD

Malfunction

reset output

circuit

Watchdog timer reset

Address trap reset

System clock reset

TENTATIVE