S

1

2

3...6

7

8

9

Start

Condition

Acknowledge Signal

from Receiver

Transmitter Stays off the

Bus During the

Acknowledge Clock

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

LP8543

www.ti.com

SNVS604D – AUGUST 2009 – REVISED MARCH 2013

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock (SCLK). LP8543 is always a slave device.

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCLK and in the middle of a transaction, aborts the current transaction.

New data should be sent during the low SCLK state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 25. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Figure 26. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCLK) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCLK is high indicates a Stop Condition.

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