DCP

(SE

Waveform)

Link Up

Idle

Link Off

Bus Phase

H

PD*

Active

CLK

Power

DCN

(SE

Waveform)

DC

(DIFF)

DDP

(SE

Waveform)

DDN

(SE

Waveform)

DD

(DIFF)

Idle

L

H

L

LM4308

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SNLS225C – AUGUST 2007 – REVISED MAY 2013

Name

DC State

DD State

Phase Description

Pre-Phase

Post-Phase

OFF (O)

GND

GND

Link is Off

A, I or LU

LU

IDLE (I)

A

H

Idle, MD(s) = Logic Low

A or LU

A or O

ACTIVE (A),

A

X

Write Payloads

LU, A, or I

A, I, or O

Write

ACTIVE,

Read Command

A

X

Read Command

A, or I

Read

(MST)

TA’

A

HUH

MD Turn Around

RC

RD

Read Data

A

X

Read Payload

TA’

TA"

(SLV)

TA"

A

HUH

MD Turn Around

RD

I

LINK-UP

Master

*

*

Start Up

O

A, I, or O

(LU)

(1)

Notes on DC/DD Line State:

0 = no current (off)

SERIAL BUS START UP TIMING

The DC and DD lines are held at a LVCMOS Low state in the Sleep state (PD* = L). When the PD* signal is

switched to a High state the DC lines are pulsed. Next the DC lines are driven to the differential levels and the

clock signal is active. The DD lines are then pulsed from a LVCMOS Low state, then driven to a valid differential

static High state. Data transmission (WRITE) starts with a valid Low start bit on the DD signal.

Figure 6. Serial Bus Power Up Timing

Actual start up time is clock rate dependant. The 1024 CLK counter encompasses both the SLVS start up delay

and PLL Lock Time. At 19.2MHz operation, the link is ready for transmission after only 54 µs. Do not WRITE to

either display before the serial link start up delay has expired.

Table 4. Start Up Time vs. CLK Frequency

CLK FREQ

Start Up Delay

9.6MHz

106.7 µs

19.2MHz

53.3 µs

30MHz

34.13 µs

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