M3062LFGPFP datasheet(56/103 Pages) RENESAS

56 / 103 page

M16C/62P Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics

Rev.2.41

Jan 10, 2006

Page 54 of 96

REJ03B0001-0241

VCC1=VCC2=5V

Switching Characteristics

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr =

−20 to 85°C / −40 to 85°C unless otherwise specified)

NOTES:

Calculated according to the BCLK frequency as follows:

This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

t =

−CR X ln (1−VOL / VCC2)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1k

Ω, hold time

of output ”L” level is

t =

−30pF X 1kΩ X In(1−0.2VCC2 / VCC2)

= 6.7ns.

Table 5.28

Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external

area access)

Symbol

Parameter

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address Output Delay Time

See

Figure 5.2

th(BCLK-AD)

Address Output Hold Time (in relation to BCLK)

th(RD-AD)

Address Output Hold Time (in relation to RD)

th(WR-AD)

Address Output Hold Time (in relation to WR)

(NOTE 2)

td(BCLK-CS)

Chip Select Output Delay Time

th(BCLK-CS)

Chip Select Output Hold Time (in relation to BCLK)

td(BCLK-ALE)

ALE Signal Output Delay Time

th(BCLK-ALE)

ALE Signal Output Hold Time

-4

td(BCLK-RD)

RD Signal Output Delay Time

th(BCLK-RD)

RD Signal Output Hold Time

td(BCLK-WR)

WR Signal Output Delay Time

th(BCLK-WR)

WR Signal Output Hold Time

td(BCLK-DB)

Data Output Delay Time (in relation to BCLK)

th(BCLK-DB)

Data Output Hold Time (in relation to BCLK) (3)

4ns

td(DB-WR)

Data Output Delay Time (in relation to WR)

(NOTE 1)

th(WR-DB)

Data Output Hold Time (in relation to WR)(3)

(NOTE 2)

td(BCLK-HLDA)

HLDA Output Delay Time

n0.5

–

()x10

fBCLK

()

------------------------------------

40 ns

[]

–

0.5x10

fBCLK

()

------------------------10 ns

[]

–

DBi

n is “1” for 1-wait setting, “2” for 2-wait setting

and “3” for 3-wait setting.

(BCLK) is 12.5MHz or less.

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