DDC101 datasheet(2/29 Pages) TI

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DDC101

TABLE OF CONTENTS

Section 1 ............. Basic Theory of Operation

2 ............. Specifications

3 ............. Pin Descriptions

4 ............. Timing Diagrams

5 ............. Discussion of Specifications

6 ............. Detailed Theory of Operation

7 ............. Applications Information

8 ............. Mechanical

The second block diagram, Figure 2, shows the DDC101

circuit architecture which implements these functions

monolithically. During each conversion, the input signal

current is collected on the internal integration capacitance,

INT, as charge for a user determined integration period, TINT.

As the integration capacitor collects input charge, the track-

ing logic updates the internal high resolution D/A converter

at a 2MHz rate to maintain the analog input node at virtual

ground.

The digital filter oversamples the tracking logic’s output at

the beginning and end of each integration period to produce

two oversampled data points. The DDC101 measures the

charge accumulated in the integration and performs corre-

lated double sampling (CDS) by subtracting these two data

points. CDS eliminates integration cycle dependent errors

such as charge injection, offset voltage, and reset noise since

these errors are measured with the signal at each of the two

data points. The number of oversamples, and thus the fre-

quency response of the digital filter, is user programmable.

The digital filter passes a low noise, high resolution digital

output to the serial I/O register. Since the timing control of

the serial I/O register is independent of the DDC101 conver-

sion process, the outputs of multiple DDC101 units can be

connected together in series or parallel to minimize intercon-

nections.

SECTION 1

BASIC THEORY OF OPERATION

The basic function of the DDC101 is illustrated in the

Simplified Equivalent Circuit shown in Figure 1. The opera-

tion is equivalent to the functions performed by a very high

quality, low bias current switched integrator followed by a

precision floating point programmable gain amplifier and

ending with a high resolution A/D converter.

FIGURE 1. Simplified Equivalent Circuit of DDC101 to Illustrate Function.

FIGURE 2. DDC101 Block Diagram.

INT

Digital Integration,

Tracking and

Control Logic

Digital Filter and

Error Correction

Serial I/O

Serial In

Serial Out

Reset

DAC

CDAC

DDC101 Integrated Circuit

Comparator

REF

Analog

Input

Ground

Setup

Oversampled

Digital Out

18 Bits

20 Bits

Test In

Test Current

INT

Data Out

Reset

Switched Integrator

Programmable Gain

Amplifier

A/D Converter

and Control Logic

Sensor

i Signal

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