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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AFE5809ZCF датащи(PDF) 13 Page - Texas Instruments |
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AFE5809ZCF датащи(HTML) 13 Page - Texas Instruments |
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13 / 90 page  AFE5809 www.ti.com SLOS738C – SEPTEMBER 2012 – REVISED JANUARY 2013 DIGITAL CHARACTERISTICS Typical values are at +25°C, AVDD = 3.3V, AVDD_5 = 5V and AVDD_ADC = 1.8V, DVDD = 1.8V unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = 0°C to TMAX = +85°C,. PARAMETER CONDITION MIN TYP MAX UNITS(1) DIGITAL INPUTS/OUTPUTS VIH Logic high input voltage 2 3.3 V VIL Logic low input voltage 0 0.3 V Logic high input current 200 µA Logic low input current 200 µA Input capacitance 5 pF VOH Logic high output voltage SDOUT pin DVDD V VOL Logic low output voltage SDOUT pin 0 V LVDS OUTPUTS with 100 ohms external differential Output differential voltage 400 mV termination Output offset voltage Common-mode voltage 1100 mV FCLKP and FCLKM 1X clock rate 10 65 MHz DCLKP and DCLKM 7X clock rate 70 455 MHz 6X clock rate 60 390 MHz tsu Data setup time(2) 350 ps th Data hold time(2) 350 ps ADC INPUT CLOCK CLOCK frequency 10 65 MSPS Clock duty cycle 45% 50% 55% Sine-wave, ac-coupled 0.5 Vpp Clock input amplitude, LVPECL, ac-coupled 1.6 Vpp differential(VCLKP_ADC–VCLKM_ADC) LVDS, ac-coupled 0.7 Vpp Common-mode voltage biased internally 1 V Clock input amplitude VCLKP_ADC (single- CMOS CLOCK 1.8 Vpp ended) (1) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1 with 100 Ω external termination. (2) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: AFE5809 |
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