RNA53A27F datasheet(3/7 Pages) RENESAS

3 / 7 page

RNA53A27F

Target Specification

R03DS0022EJ0300 Rev.3.00

Page 3 of 6

Jun 26, 2013

Pin Arrangement

ROSC

SLP

VOUT

VREFO

VDD

GND

(Top view)

Mark Indication

(1) (2) (3)

N 0 2

(1)

Year code

The last digit of year

(2)

Month code

Starting in January "A", "B", "C", "D", "E", "F", "G", "H", "J", "K", "L", "M"

(3)

Week code

View week of month, 1 week

→ "1"

Pin Description

Pin No.

Terminal

Marking

Terminal Name

I/O

Function

ROSC

Oscillation control resistance

installation terminal

—

• 1.1 MΩ is installed between GND usually.

• Delay adjustment range of resistance: 650(kΩ) to 1.35(MΩ)

SLP

Sleep mode control

• L: Sleep mode (Power-supply current becomes several μA)

• H: Usually mode

• Terminal is open, Pull-down in GND

Manual reset input

• Low is input, 5pin(VOUT) output the low level

Set the low pulse width by value is longer 3

μs

• Terminal open, pull-up in VDD

GND

—

• Sorcing 0 V.

VOUT

Reset output

• Power-supply voltage reaches the value below the detection

voltage, low is output

• Low level is input to MR terminal, low is output

• Open drain output

• Range pull-up resistance: 10(kΩ) to 100(kΩ)

VREFO

Standard voltage output

• Standard voltage (3.05 V typ) for AD/DA is output

• Outside puts capacity (0.1 μF) by pursuant for microcomputer

VDD

Power-supply terminal

—

• Sorcing power-supply voltage.

Delay time switch

• Delay time is switched. Low: 50 (ms), High: 100 (ms)

• Terminal is open, pull-up in Vdd

RNA53A27F датащи(PDF) 3 Page - Renesas Technology Corp

RNA53A27F датащи(HTML) 3 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7

датащи скачать

ссылки URL