74HC_HCT259

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 5 — 7 August 2012

3 of 22

NXP Semiconductors

74HC259; 74HCT259

8-bit addressable latch

5.

Pinning information

5.1 Pinning

Fig 3.

Functional diagram

mna571

8 LATCHES

1-of-8

DECODER

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

12

11

10

9

7

6

5

4

A0

A1

A2

LE

MR

D

13

15

14

3

2

1

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as

supply pin or input.

Fig 4.

Pin configuration (DIP16, SO16, SSOP16 and

TSSOP16)

Fig 5.

Pin configuration (DHVQFN16)

74HC259

74HCT259

A0

A1

MR

A2

LE

Q0

D

Q1

Q7

Q2

Q6

Q3

Q5

GND

Q4

001aaj444

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

001aaj445

74HC259

74HCT259

Q3

Q5

Q2

Q6

Q1

Q7

Q0

D

A2

LE

A1

MR

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area