Revision: 2.85

Specification Update

September 2012

14

The 82576 complies with the PCIe 2.0 Specification for the completion timeout

mechanism and programmable timeout values. The PCIe 2.0 Specification provides

programmable timeout ranges between 50us to 64s with a default time range of 50us-

50ms. The 82576 defaults to a range of 500us – 1ms for PCIe capabilities version 1 and

2. The PCIe 2.0 Specification also strongly recommends that the default timeout value be

such that the completion timeout mechanism not expire in less than 10ms.

The completion timeout value must be programmed correctly in PCIe configuration space

(in Device Control 2 Register); the value must be set above the expected maximum

latency for completions in the system in which the 82576 is installed. This will ensure that

the 82576 receives the completions for the requests it sends out, avoiding a completion

timeout scenario. Failure to properly set the completion timeout value can result in the

device timing out prior to a completion returning. In the event of a completion timeout,

the device assumes the original completion is lost, and resends the original request, by

default. In this condition, if the completion for the original request arrives at the 82576

device, this will result in 2 completions arriving for the same request, which may cause

unpredictable system behavior.

As long as the Completion Timeout value is properly programmed by the system the

completion timeout mechanism works without issue. It is expected that the system BIOS

will set this value appropriately for the system.

Workaround: Alternatively a device driver could ensure the completion timeout value is set above 10ms

(in order to follow the recommendation of the PCIe 2.0 specification). The driver would

modify the timeout value, if and only if the default timeout value remains in configuration

space. This will not impact BIOSs already changing the timeout value since the driver will

not override any non-default setting of the timeout value. For extra protection against

unpredictable system behavior in case the timeout setting is incorrect, it is recommended

to disable the resend of the request. This can be done by clearing the

Completion_Timeout_Resend bit in the GCR Register.

The latest Intel drivers implement this workaround by modifying the completion timeout

value in config space if the timeout value is still set to a value of 0x0 when the driver

loads. They also clear the Completion_Timeout_Resend bit in the GCR Register.

Release 14.4 includes this fix.

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4. PCIe: Receiver Dtection Circuit Design and Established Link Width

Clarification: The 82576 receiver detection circuit was designed according to the PCIe Specification

Rev. 1.1, which requires that an un-terminated receiver have an input impedance of at

least 200 Kohm. PCIe Specification Rev. 2.0 allows the input impedance to be as low as 1

Kohm at input voltages in the range -150 - 0 mV and does not specify a minimum input

impedance below -150 mV. As a result, a powered-down receiver lane with low input

impedance at negative voltages could be compliant to Rev 2.0 and yet be falsely detected

by the 82576 as a terminated lane.

This is normally not an issue since any connnected lanes should be properly terminated

within 5 ms after fundamental reset according to the PCIe Specification. However, there

are some chipset devices that require significantly more time to prepare the termination

and expect the link partner to remain in the LTSSM Detect state as long as none of the

lanes are terminated. When used with such devices, the 82576 might falsely detect a

receiver on one or more lanes and leave the Detect state. This can lead to establishing a

link that is less than full width.

In this case, it is recommended that a Hot Reset be performed after a link has been

established in order to force the 82576 to detect the receivers again when they are

properly terminated. As a result, a full-width link can be established.

Workaround: Not Applicable.

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