AD9979BCPZ datasheet(13/56 Pages) AD

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AD9979

Rev. C | Page 13 of 56

PROGRAMMABLE TIMING GENERATION

PRECISION TIMING HIGH SPEED TIMING CORE

The AD9979 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for

generating the timing for both the CCD and the AFE; the reset

gate (RG), the HL, Horizontal Driver H1 to Horizontal Driver

H4, and the SHP and SHD sample clocks. A unique architecture

makes it routine for the system designers to optimize image

quality by providing precise control over the horizontal CCD

readout and the AFE-correlated double sampling.

Timing Resolution

The Precision Timing core uses a master clock input (CLI) as a

reference. This clock is recommended to be the same as the

CCD pixel clock frequency. Figure 15 illustrates how the internal

timing core divides the master clock period into 64 steps, or

edge positions. Therefore, the edge resolution of the Precision

Timing core is tCLI/64. (For more information on using the

CLI input, refer to the Applications Information section.)

Using a 65 MHz CLI frequency, the edge resolution of the

Precision Timing core is approximately 240 ps. If a 1× system

clock is not available, it is also possible to use a 2× reference

clock, by programming the CLIDIVIDE register (Address 0x0D).

The AD9979 then internally divides the CLI frequency by 2.

High Speed Clock Programmability

Figure 16 shows how the high speed clocks, RG, HL, H1 to H4,

SHP, and SHD, are generated. The RG pulse has programmable

rising and falling edges and can be inverted using the polarity

control. The HL, H1, and H2 horizontal clocks have separate

programmable rising and falling edges and polarity control. The

AD9979 provides additional HCLK mode programmability, see

Table 8.

The edge location registers are each six bits wide, allowing the

selection of all 64 edge locations. Figure 19 shows the default

timing locations for all of the high speed clock signals.

P[0]

P[64] = P[0]

P[16]

P[32]

P[48]

1 PIXEL

PERIOD

CLI

tCLIDLY

POSITION

NOTES

1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (

tCLIDLY).

tCONV

Figure 15. High Speed Clock Resolution From CLI Master Clock Input

CCD

SIGNAL

PROGRAMMABLE CLOCK POSITIONS:

1SHP SAMPLE LOCATION.

2SHD SAMPLE LOCATION.

3RG RISING EDGE.

4RG FALLING EDGE.

5H1 RISING EDGE.

6H1 FALLING EDGE.

7HL RISING EDGE.

8HL FALLING EDGE.

H2, H4

H1, H3

Figure 16. High Speed Clock Programmable Locations (HCLKMODE = 1)

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