AD5764CSUZ datasheet(18/28 Pages) AD

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AD5764

Data Sheet

Rev. F | Page 18 of 28

THEORY OF OPERATION

The AD5764 is a quad, 16-bit, serial input, bipolar voltage output

DAC and operates from supply voltages of ±11.4 V to ±16.5 V and

has a buffered output voltage of up to ±10.5263 V. Data is written to

the AD5764 in a 24-bit word format, via a 3-wire serial interface.

The device also offers an SDO pin that is available for daisy-

chaining or readback.

The AD5764 incorporates a power-on reset circuit, which ensures

that the data register powers up loaded with 0x0000. The AD5764

features a digital I/O port that can be programmed via the serial

interface, on-chip reference buffers and per channel digital gain,

and offset registers.

DAC ARCHITECTURE

The DAC architecture of the AD5764 consists of a 16-bit,

current mode, segmented R-2R DAC. The simplified circuit

diagram for the DAC section is shown in Figure 32.

The four MSBs of the 16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

the 15 matched resistors to either AGNDx or IOUT. The remain-

ing 12 bits of the data-word drive Switch S0 to Switch S11 of

the 12-bit R-2R ladder network.

E15

VREF

E14

S11

S10

12-BIT, R-2R LADDER

4 MSBs DECODED INTO

15 EQUAL SEGMENTS

VOUTx

AGNDx

R/8

IOUT

Figure 32. DAC Ladder Structure

REFERENCE BUFFERS

The AD5764 operates with an external reference. The reference

inputs (REFAB and REFCD) have an input range up to 7 V. This

input voltage is used to provide a buffered positive and negative

reference for the DAC cores. The positive reference is given by

+VREF = 2 × VREF

The negative reference to the DAC cores is given by

−VREF = −2 × VREF

These positive and negative reference voltages (along with the

gain register values) define the output ranges of the DACs.

SERIAL INTERFACE

The AD5764 is controlled over a versatile 3-wire serial interface

that operates at clock rates of up to 30 MHz and is compatible

with SPI, QSPI™, MICROWIRE™, and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. The input shift register consists of a read/

write bit, three register select bits, three DAC address bits, and

16 data bits, as shown in Table 9. The timing diagram for this

operation is shown in Figure 2.

Upon power-up, the data register is loaded with zero code

(0x0000), and the outputs are clamped to 0 V via a low imped-

ance path. The outputs can be updated with the zero code value

at this time by asserting either LDAC or CLR. The corresponding

output voltage depends on the state of the BIN/2sCOMP pin. If

the BIN/2sCOMP pin is tied to DGND, the data coding is twos

complement, and the outputs update to 0 V. If the BIN/2sCOMP

pin is tied to DVCC, the data coding is offset binary, and the

outputs update to negative full scale. To power up the outputs

with zero code loaded to the outputs, hold the CLR pin low

during power-up.

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can only be

used if SYNC is held low for the correct number of clock cycles.

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used and SYNC must be taken high after

the final clock to latch the data. The first falling edge of SYNC

starts the write cycle. Exactly 24 falling clock edges must be

applied to SCLK before SYNC is brought high again. If SYNC is

brought high before the 24th falling SCLK edge, the data written

is invalid. If more than 24 falling SCLK edges are applied before

SYNC is brought high, the input data is also invalid. The input

shift register addressed is updated on the rising edge of SYNC.

For another serial transfer to take place, SYNC must be brought

low again. After the end of the serial data transfer, data is

automatically transferred from the input shift register to the

addressed register.

When the data has been transferred into the chosen register of

the addressed DAC, the data register and outputs can be

updated by taking LDAC low.

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