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CYUSB301X

Document Number: 001-52136 Rev. *N

Page 29 of 45

Asynchronous Slave FIFO Read Sequence

Description

■ FIFO address is stable and the SLCS# signal is asserted.

■ SLOE# is asserted. This results in driving the data bus.

■ SLRD # is asserted.

■ Data from the FIFO is driven after assertion of SLRD#. This

data is valid after a propagation delay of tRDO from the falling

edge of SLRD#.

■ FIFO pointer is incremented on deassertion of SLRD#

In Figure 14, data N is the first valid data read from the FIFO. For

data to appear on the data bus during the read cycle, SLOE#

must be in an asserted state. SLRD# and SLOE# can also be

tied.

The same sequence of events is also shown for a burst read.

Note In the burst read mode, during SLOE# assertion, the data

bus is in a driven state (data is driven from a previously

addressed FIFO). After assertion of SLRD# data from the FIFO

is driven on the data bus (SLOE# must also be asserted). The

FIFO pointer is incremented after deassertion of SLRD#.

Table 11. Synchronous Slave FIFO Parameters[7]

Parameter

Description

Min

Max

Units

FREQ

Interface clock frequency

–

100

MHz

tCYC

Clock period

–

tCH

Clock high time

–

tCL

Clock low time

–

tRDS

SLRD# to CLK setup time

–

tRDH

SLRD# to CLK hold time

0.5

–

tWRS

SLWR# to CLK setup time

–

tWRH

SLWR# to CLK hold time

0.5

–

tCO

Clock to valid data

–

tDS

Data input setup time

–

tDH

CLK to data input hold

0.5

–

tAS

Address to CLK setup time

–

tAH

CLK to address hold time

0.5

–

tOELZ

SLOE# to data low-Z

–

tCFLG

CLK to flag output propagation delay

–

tOEZ

SLOE# deassert to Data Hi Z

–

tPES

PKTEND# to CLK setup

–

tPEH

CLK to PKTEND# hold

0.5

–

tCDH

CLK to data output hold

–

Note Three-cycle latency from ADDR to DATA/FLAGS

Note

7. All parameters guaranteed by design and validated through characterization.

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