CYUSB3035 datasheet(21/50 Pages) CYPRESS

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CYUSB3035

Document Number: 001-84160 Rev. *B

Page 21 of 50

VOH

Output HIGH voltage

0.9 × VCC

–

IOH (max) = –100 µA tested at

quarter drive strength. VCC is

the corresponding I/O voltage

supply.

VOL

Output LOW voltage

–

0.1 × VCC

IOL (min) = +100 µA tested at

quarter drive strength. VCC is

the corresponding I/O voltage

supply.

IIX

Input leakage current for all pins except

SSTXP/SSXM/SSRXP/SSRXM

–1

µA

All I/O signals held at VDDQ

(For I/Os with a pull-up or

pull-down resistor connected,

the leakage current increases

by VDDQ/Rpu or VDDQ/RPD

IOZ

Output High-Z leakage current for all

pins except SSTXP/ SSXM/

SSRXP/SSRXM

–1

µA

All I/O signals held at VDDQ

ICC Core

Core and analog voltage operating

current

–

200

Total current through AVDD,

VDD

ICC USB

USB voltage supply operating current

–

ISB1

Total suspend current during suspend

mode with USB 3.0 PHY enabled (L1)

–

Core current: 1.5 mA

I/O current: 20 µA

USB current: 2 mA

For typical PVT (typical silicon,

all power supplies at their

respective nominal levels at

25 °C.)

ISB2

Total suspend current during suspend

mode with USB 3.0 PHY disabled (L2)

–

Core current: 250 µA

I/O current: 20 µA

USB current: 1.2 mA

For typical PVT (Typical

silicon, all power supplies at

their respective nominal levels

at 25 °C.)

ISB3

Total standby current during standby

mode (L3)

–

µA

Core current: 60 µA

I/O current: 20 µA

USB current: 40 µA

For typical PVT (typical silicon,

all power supplies at their

respective nominal levels at

25 °C.)

ISB4

Total standby current during core

power-down mode (L4)

–

µA

Core current: 0 µA

I/O current: 20 µA

USB current: 40 µA

For typical PVT (typical silicon,

all power supplies at their

respective nominal levels at

25 °C.)

VRAMP

Voltage ramp rate on core and I/O

supplies

0.2

V/ms

Voltage ramp must be

monotonic

Noise level permitted on VDD and I/O

supplies

–

100

Max p-p noise level permitted

on all supplies except AVDD

VN_AVDD

Noise level permitted on AVDD supply

–

Max p-p noise level permitted

on AVDD

Table 7. DC Specifications

(continued)

Parameter

Description

Min

Max

Units

Notes

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