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CY62156ESL датащи(PDF) 7 Page - Cypress Semiconductor

номер детали CY62156ESL
подробное описание детали  8-Mbit (512 K x 16) Static RAM
PDF  16 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62156ESL датащи(HTML) 7 Page - Cypress Semiconductor

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CY62156ESL MoBL®
Document Number: 001-54995 Rev. *D
Page 7 of 16
Switching Characteristics
Over the Operating Range
Parameter [13]
Description
45 ns
Unit
Min
Max
Read Cycle
tRC
Read Cycle Time
45
–
ns
tAA
Address to Data Valid
–
45
ns
tOHA
Data Hold from Address Change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
–
45
ns
tDOE
OE LOW to Data Valid
–
22
ns
tLZOE
OE LOW to Low Z[14]
5
–
ns
tHZOE
OE HIGH to High Z[14, 15]
–
18
ns
tLZCE
CE1 LOW and CE2 HIGH to Low Z[14]
10
–
ns
tHZCE
CE1 HIGH and CE2 LOW to High Z[14, 15]
–
18
ns
tPU
CE1 LOW and CE2 HIGH to Power Up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to Power Down
–
45
ns
tDBE
BLE/BHE LOW to Data Valid
–
22
ns
tLZBE
BLE/BHE LOW to Low Z[14]
5
–
ns
tHZBE
BLE/BHE HIGH to High Z[14, 15]
–
18
ns
Write Cycle[16]
tWC
Write Cycle Time
45
–
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
–
ns
tAW
Address Setup to Write End
35
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Setup to Write Start
0
–
ns
tPWE
WE Pulse Width
35
–
ns
tBW
BLE/BHE LOW to Write End
35
–
ns
tSD
Data Setup to Write End
25
–
ns
tHD
Data Hold from Write End
0
–
ns
tHZWE
WE LOW to High Z[14, 15]
–
18
ns
tLZWE
WE HIGH to Low Z[14]
10
–
ns
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.



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