STPMS2

Theory of operation

Doc ID 16525 Rev 3

27/33

8.5.1

Writing to the configuration register in Soft mode

All 40 configuration bits must be overwritten.

1.

After power-on reset, Soft mode is selected (MS3=CLK), the bits MS0 .. MS2 must be stable at least 5*CLK

2.

After switching into Soft mode (MS3=CLK), the bits MS0 .. MS2 must be stable at least 2*CLK. The same

rule applies when switching from Soft mode to Hard mode: MS0 .. MS2 must be stable at least 2*CLK

Figure 20.

Timings to switch to Soft mode after POR

AM09897v1

NEW values

CLK

MS1/TDI

MS0/SCL

MS2/TDS

CFG[0]

CFG[1]

CFG[2]

CFG[38]

CFG[39]

MS3/CLK

CFG

Figure 21.

Timings to switch to Soft mode

AM09898v1

NEW values

CLK

MS1/TDI

MS0/SCL

MS2/TDS

CFG[1]

CFG[2]

CFG[3]

CFG[38]

CFG[39]

MS3/CLK

CFG

CFG[0]

OLD values

Hard Mode