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6.5.2

Display Subsystem (DSS)

6.5.2.1 LCD Display in Bypass Mode

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or

internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller, a remote

frame buffer module (RFBI), and a TV-out module. It can be used in two configurations:

• LCD display in:

–

Bypass mode (RFBI module bypassed)

–

RFBI mode (through RFBI module)

• TV display (not discussed in this document because of its analog IO signals)

The two displays can be active at the same time.

NOTE

For more information, see Display Subsystem / Display Subsystem Functional Description

section of the OMAP35x Technical Reference Manual (TRM) [literature number

SPRUF98.

Two types of LCD panel are supported:

• Thin film transistor (TFT) or active matrix technology

• Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

6.5.2.1.1 LCD Display in TFT Mode

6.5.2.1.1.1 LCD Display in TFT Mode – HDTV Application

Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-28).

Table 6-37. LCD Display Switching Characteristics in TFT Mode – HDTV Application(3)(4)

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

DL0

td(PCLKA-HSYNCT) Delay time, dss_pclk active edge to dss_hsync

–4.2

4.2

–4.7

4.7

transition

DL1

td(PCLKA-VSYNCT)

Delay time, dss_pclk active edge to dss_vsync

–4.2

4.2

–4.7

4.7

transition

DL2

td(PCLKA-ACBIASA) Delay time, dss_pclk active edge to

–4.2

4.2

–4.7

4.7

dss_acbias active level

DL3

td(PCLKA-DATAV)

Delay time, dss_pclk active edge to dss_data

–4.2

4.2

–4.7

4.7

bus valid

DL4

tc(PCLK)

Cycle time(2), dss_pclk

13.468

15.152

DL5

tw(PCLK)

Pulse duration, dss_pclk low or high

0.45*P(1)

0.55*P(1)

0.45*P(1)

0.55*P(1)

(1) P = dss_pclk period.

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) The capacitive load is equivalent to 25 pF at 1.15 V and 30 pF at 1.0 V.

(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98.

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