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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F050C4 датащи(PDF) 15 Page - STMicroelectronics |
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STM32F050C4 датащи(HTML) 15 Page - STMicroelectronics |
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15 / 97 page  STM32F050xx Functional overview Doc ID 023683 Rev 1 15/97 3.6 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz. Figure 2. Clock tree |
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