PIC24FJ128GA006-IPT datasheet(116/258 Pages) MICROCHIP

116 / 258 page

PIC24FJ128GA010 FAMILY

DS39747F-page 116

 2005-2012 Microchip Technology Inc.

TxCON: TIMER2 AND TIMER4 CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

TON

—TSIDL

—

bit 15

bit 8

U-0

R/W-0

U-0

R/W-0

U-0

—

TGATE

TCKPS1

TCKPS0

T32(1)

—TCS

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

TON:

Timerx On bit

When TxCON<3> = 1:

= Starts 32-bit Timerx/y

= Stops 32-bit Timerx/y

When TxCON<3> = 0:

= Starts 16-bit Timerx

= Stops 16-bit Timerx

bit 14

Unimplemented:

Read as ‘0’

bit 13

TSIDL:

Stop in Idle Mode bit

= Discontinues module operation when the device enters Idle mode

= Continues module operation in Idle mode

bit 12-7

Unimplemented:

Read as ‘0’

bit 6

TGATE:

Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

= Gated time accumulation is enabled

= Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>:

Timer2 Input Clock Prescale Select bits

= 1:256

= 1:64

= 1:8

= 1:1

bit 3

T32:

32-Bit Timer Mode Select bit(1)

= Timerx and Timery form a single 32-bit timer

= Timerx and Timery act as two 16-bit timers

bit 2

Unimplemented:

Read as ‘0’

bit 1

TCS:

Timerx Clock Source Select bit

= External clock from pin, TxCK (on the rising edge)

= Internal clock (FOSC/2)

bit 0

Unimplemented:

Read as ‘0’

Note 1:

In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.

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