PIC24FJ128GA006-IPT datasheet(98/258 Pages) MICROCHIP

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PIC24FJ128GA010 FAMILY

DS39747F-page 98

 2005-2012 Microchip Technology Inc.

8.1

CPU Clocking Scheme

The system clock source can be provided by one of

four sources:

• Primary Oscillator (POSC) on the OSC1 and

OSC2 pins

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

The primary oscillator and FRC sources have the

option of using the internal 4x PLL. The frequency of

the FRC clock source can optionally be reduced by the

programmable clock divider. The selected clock source

generates the processor and peripheral clock sources.

The processor clock source is divided by two to pro-

duce the internal instruction cycle clock, FCY. In this

document, the instruction cycle clock is also denoted

by FOSC/2. The internal instruction cycle clock, FOSC/2,

can be provided on the OSC2 I/O pin for some

operating modes of the primary oscillator.

8.2

Oscillator Configuration

The oscillator source (and operating mode) that is

used at a device Power-on Reset event is selected

using Configuration bit settings. The oscillator Config-

uration bit settings are located in the Configuration

registers

the

program

memory

(refer

Section 24.1

“Configuration

Bits”

for further

details). The Primary Oscillator Configuration bits,

POSCMD<1:0> (Configuration Word 2<1:0>), and

the Initial Oscillator Select Configuration bits,

FNOSC<2:0> (Configuration Word 2<10:8>), select

the oscillator source that is used at a Power-on Reset.

The FRC primary oscillator with postscaler (FRCDIV)

is the default (unprogrammed) selection. The second-

ary oscillator, or one of the internal oscillators, may be

chosen by programming these bit locations.

The Configuration bits allow users to choose between

the various clock modes, shown in Table 8-1.

8.2.1

CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (Configuration Word 2<7:6>)

are used to jointly configure device clock switching and

the Fail-Safe Clock Monitor (FSCM). Clock switching is

enabled only when FCKSM1 is programmed (‘0’). The

FSCM is enabled only when FCKSM<1:0> are both

programmed (‘00’).

TABLE 8-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode

Oscillator Source

POSCMD<1:0>

FNOSC<2:0>

Note

Fast RC Oscillator with Postscaler

(FRCDIV)

Internal

111

1, 2

(Reserved)

Internal

110

Low-Power RC Oscillator (LPRC)

Internal

101

Secondary (Timer1) Oscillator

(SOSC)

Secondary

100

Primary Oscillator (HS) with PLL

Module (HSPLL)

Primary

011

Primary Oscillator (XT) with PLL

Module (XTPLL)

Primary

011

Primary Oscillator (EC) with PLL

Module (ECPLL)

Primary

011

Primary Oscillator (HS)

Primary

010

Primary Oscillator (XT)

Primary

010

Primary Oscillator (EC)

Primary

010

Fast RC Oscillator with PLL Module

(FRCPLL)

Internal

001

Fast RC Oscillator (FRC)

Internal

000

Note 1:

OSC2 pin function is determined by the OSCIOFNC Configuration bit.

This is the default oscillator mode for an unprogrammed (erased) device.

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