74LVC02A

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Product data sheet

Rev. 8 — 16 November 2011

3 of 14

NXP Semiconductors

74LVC02A

Quad 2-input NOR gate

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care

7.

Limiting values

[1]

The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2]

The output voltage ratings may be exceeded if the output current ratings are observed.

[3]

For SO14 packages: above 70

C derate linearly with 8 mW/K.

For (T)SSOP14 packages: above 60

C derate linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60

C derate linearly with 4.5 mW/K.

Table 2.

Pin description

Symbol

Pin

Description

1Y to 4Y

1, 4, 10, 13

data output

1A to 4A

2, 5, 8, 11

data input

1B to 4B

3, 6, 9,12

data input

GND

7

ground (0 V)

14

supply voltage

Table 3.

Function table[1]

Input nA

Input nB

Output nY

LLH

XH

L

HX

L

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.5

+6.5

V

input clamping current

50

-

mA

input voltage

[1]

0.5

+6.5

V

output clamping current

-

50

mA

output voltage

output in HIGH or LOW-state

[2]

0.5

V

output current

-

50

mA

supply current

-

100

mA

ground current

100

-

mA

total power dissipation

[3] -

500

mW

storage temperature

65

+150

C