CDC3RL02 datasheet(4/15 Pages) TI

4 / 15 page

CDC3RL02

SCHS371 – NOVEMBER 2009

www.ti.com

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LDO

VOUT

LDO output voltage

IOUT = 50 mA

1.71

1.8

1.89

CLDO

External load capacitance

μF

IOUT(SC)

Short circuit output current

RL = 0 Ω

100

I0UT(PK)

Peak output current

VBATT = 2.3 V, VLDO = VOUT – 5%

100

fIN = 217 Hz and

1 kHz

PSR

Power supply rejection

VBATT = 2.3V, IOUT = 2 mA,

fIN = 3.25 MHz

VBATT = 2.3 V , CLDO = 1 μF, CLK_REQ_n to

0.2

VLDO = 1.71 V

tsu

LDO startup time

VBATT = 5.5 V , CLDO = 10 μF, CLK_REQ_n to

VLDO = 1.71 V

Power Consumption

ISB

Standby current

Device in standby (all VCLK_REQ_n = 0 V)

0.2

μA

ICCS

Static current consumption

Device active but not switching

0.4

IOB

Output buffer average current

fIN = 26 MHz, CLOAD = 50 pF

4.2

Output power dissipation

CPD

fIN = 26 MHz

capacitance

MCLK_IN Input

MCLK_IN, CLK_REQ_1/2

VI = VLDO or GND

μA

leakage current

MCLK_IN capacitance

fIN = 26 MHz

4.75

MCLK_IN impedance

fIN = 26 MHz

Ω

fIN

MCLK_IN frequency range

MHz

MCLK_IN LVCMOS Source

1-kHz offset

–140

10-kHz offset

–149

Additive phase noise

fIN = 26 MHz, tr/tf ≤ 1 ns

dBc/Hz

100-kHz offset

–153

1-MHz offset

–148

Additive jitter

fIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz

0.37

ps (rms)

MCLK_IN to CLK_OUT_n

tDL

propagation delay

DCL

Output duty cycle

fIN = 26 MHz, DCIN = 50%

Submit Documentation Feedback

Product Folder Link(s): CDC3RL02

CDC3RL02 датащи(PDF) 4 Page - Texas Instruments

CDC3RL02 датащи(HTML) 4 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

датащи скачать

ссылки URL