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CC1150-RTR1 датащи(PDF) 57 Page - Texas Instruments |
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CC1150-RTR1 датащи(HTML) 57 Page - Texas Instruments |
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57 / 67 page ![]() CC1150 SWRS037A Page 57 of 60 26 Package Description (QLP 16) 26.1 Recommended PCB layout for package (QLP 16) Figure 24: Recommended PCB layout for QLP 16 package Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC1150EM reference design ([1] and [2]). 26.2 Soldering information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed. |
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