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ADRF6806ACPZ-R7 датащи(PDF) 27 Page - Analog Devices |
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ADRF6806ACPZ-R7 датащи(HTML) 27 Page - Analog Devices |
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27 / 36 page ![]() Data Sheet ADRF6806 Rev. B | Page 27 of 36 The package for the ADRF6806 features an exposed paddle on the underside that should be well soldered to an exposed opening in the solder mask on the evaluation board. Figure 45 illustrates the dimensions used in the layout of the ADRF6806 footprint on the ADRF6806 evaluation board (1 mil. = 0.0254 mm). Note the use of nine via holes on the exposed paddle. These ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. Under these conditions, the thermal impedance of the ADRF6806 was measured to be approximately 30°C/W in still air. 0.168 0.232 0.177 0.035 0.050 0.012 0.025 0.020 Figure 45. Evaluation Board Layout Dimensions for the ADRF6806 Package Figure 46. ADRF6806 Evaluation Board Top Layer Figure 47. ADRF6806 Evaluation Board Bottom Layer |
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