MCP3911 datasheet(39/72 Pages) MICROCHIP

39 / 72 page

DS22286A-page 39

MCP3911

5.7.3

TEMPERATURE COMPENSATION

(VREFCAL REGISTER)

The internal voltage reference comprises a proprietary cir-

cuit and algorithm to compensate first order and second

order temperature coefficients. The compensation allows

very low temperature coefficients (typically 7 ppm/°C) on

the entire range of temperatures from -40°C to 125°C.

This temperature coefficient varies from part to part.

This temperature coefficient can be adjusted on each

part through the VREFCAL register (address 0x1A).

This register is only for advanced users. This register

should not be written unless the user wants to calibrate

the temperature coefficient of the whole system or

application. The default value of this register is set to

0x42. The typical variation of the temperature coeffi-

cient of the internal voltage reference, with respect to

VREFCAL register code, is given by Figure 5-6. Modi-

fying the value stored in the VREFCAL register may

also vary the output voltage, in addition to the

temperature coefficient.

FIGURE 5-6:

VREF Tempco vs. VREFCAL

Trimcode Chart.

5.8

Power-on Reset

The MCP3911 contains an internal POR circuit that

monitors both analog and digital supply voltages during

operation. The typical threshold for a power-up event

detection is 2.1 V ±5% and a typical start-up time (tPOR)

of 50 µs. The POR circuit has a built-in hysteresis for

improved transient spikes immunity that has a typical

value of 200 mV. Proper decoupling capacitors (0.1 µF

ceramic and 10 µF tantalum) should be mounted as

close as possible to the AVDD and DVDD pins, providing

additional transient immunity.

Figure 5-7

illustrates

the

different

conditions

power-up

and

power-down

event

typical

conditions. All internal DC biases are not settled until at

least 1 ms, in worst case conditions, after system POR.

Any data ready pulse that occurs within 1 ms, plus the

sinc filter settling time after system reset, should be

ignored to guarantee proper accuracy. After POR, data

ready pulses are present at the pin with all the default

conditions in the configuration registers.

Both AVDD and DVDD are monitored so either power

supply can sequence first.

FIGURE 5-7:

Power-on Reset Operation.

128

192

256

VREFCAL Register Trim Code (decimal)

POR

State

Power-Up

Normal Operation

POR

State

Biases are

unsettled.

Conversions

started here may

not be accurate.

Biases are settled.

Conversions started

here are accurate.

Analog biases

settling time

SINC filter

settling

time

Any data read pulse occuring during this

time can yield inaccurate output data. It is

recommended to discard them.

Voltage

(AVDD, DVDD)

Time

POR Threshold

up (2.1V typ.)

(1.9V typ.)

tPOR

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