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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT45FH4M датащи(PDF) 9 Page - Holtek Semiconductor Inc |
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HT45FH4M датащи(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 138 page  Rev. 1.10 8 �an�a�� 1�� �01� Rev. 1.10 9 �an�a�� 1�� �01� HT45FH4M Lithium Battery Backup Power ASSP MCU HT45FH4M Lithium Battery Backup Power ASSP MCU Pin Description Withtheexceptionofthepowerpinsandsomerelevanttransformercontrolpins,allpinsonthese devicescanbereferencedbytheirPortname,e.g.PA.0,PA.1etc,whichrefertothedigitalI/O functionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchastheAnalog toDigitalConverter,TimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable, howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet. Pin Name Function OPT I/T O/T Pin-Shared Mapping PA0~PA7 Gene�al p��pose I/O po�t A PAPU PAWU ST CMOS — PB0~PB�� PB6~PB7 Gene�al p��pose I/O po�t B PBPU ST CMOS — OVP Ove� voltage p�otection inp�t OCVPR1 AN — PA0 OCP Ove� c���ent p�otection inp�t OCVPR1 AN — PA� DAPWR D/A Conve�te� powe� inp�t OCVPR0 PWR — PA1 AN0~AN7 A/D Conve�te� inp�t 0~7 ADCR0 ACERL AN — PA0~PA7 VREF A/D Conve�te� �efe�ence voltage inp�t ADCR1 AN — PA1 INT0� INT1 Exte�nal inte���pt 0� 1 INTEG INTC0 INTC� ST — PA�� PA6 TCK0� TCK1 TM0� TM1 inp�t — ST — PA�� PA6 TP0_0� TP0_1 TM0 I/O TMPC ST CMOS PA7� PB0 TP1_1 TM1 I/O TMPC ST CMOS PB1 ICPCK In-ci�c�it p�og�amming clock pin — ST — PA7 ICPDA In-ci�c�it p�og�amming data/add�ess pin — ST CMOS PA6 OCDSCK On-chip deb�g s�ppo�t clock pin — ST — PA7 OCDSDA On-chip deb�g s�ppo�t data/add�ess pin — ST CMOS PA6 V� �V LDO o�tp�t — — PWR — VCC �V LDO powe� s�ppl� and Level shift o�tp�t d�iving powe� — PWR — — VDD Positive powe� s�ppl� — PWR — — VSS Negative powe� s�ppl�� g�o�nd — PWR — — AX� BX� CX� DX Level shift o�tp�ts — — — — Internal Connection Description Signal Name Function OPT I/T O/T Pin-Shared Mapping PB�~PB� Gene�al p��pose inp�t/o�tp�t. Registe� enabled p�ll-�p. Inte�nall� connected to the level shift inp�ts �espectivel� and level shift enable. PBPU ST CMOS — OUTL� OUTH PWM o�tp�t Inte�nall� connected to the level shift inp�ts A and C TMPC — CMOS PB4� PB� A� C Level shift inp�ts Inte�nall� connected to PB�/OUTL and PB4/OUTH �espectivel� — — — — ENBF Level shift enable Inte�nall� connected to PB�/TP1_0 — — — — Note:I/T:Inputtype; O/T:Outputtype OPT:Optionalbyconfigurationoption(CO)orregisteroption PWR:Power; ST:SchmittTriggerinput CMOS:CMOSoutput; AN:Analogsignal |
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