LAN8710AI datasheet(11/82 Pages) SMSC

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Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

Datasheet

SMSC LAN8710A/LAN8710Ai

Revision 1.4 (08-23-12)

DATASHEET

Receive

Data 0

RXD0

VO8

Bit 0 of the 4 (2 in RMII Mode) data bits that are

sent by the transceiver on the receive path.

PHY

Operating

Mode 0

Configuration

Strap

MODE0

VIS

(PU)

Combined with MODE1 and MODE2, this

configuration strap sets the default PHY mode.

See Note 2.1 for more information on

configuration straps.

Note:

Refer to Section 3.7.2, "MODE[2:0]:

Mode Configuration," on page 36 for

additional details.

Receive

Data 1

RXD1

VO8

Bit 1 of the 4 (2 in RMII Mode) data bits that are

sent by the transceiver on the receive path.

PHY

Operating

Mode 1

Configuration

Strap

MODE1

VIS

(PU)

Combined with MODE0 and MODE2, this

configuration strap sets the default PHY mode.

See Note 2.1 for more information on

configuration straps.

Note:

Refer to Section 3.7.2, "MODE[2:0]:

Mode Configuration," on page 36 for

additional details.

Receive

Data 2

(MII Mode)

RXD2

VO8

Bit 2 of the 4 (in MII Mode) data bits that are sent

by the transceiver on the receive path.

Note:

This signal is not used in RMII Mode.

MII/RMII

Mode Select

Configuration

Strap

RMIISEL

VIS

(PD)

This configuration strap selects the MII or RMII

mode of operation. When strapped low to VSS,

MII Mode is selected. When strapped high to

VDDIO RMII Mode is selected.

See Note 2.1 for more information on

configuration straps.

Note:

Refer to Section 3.7.3, "RMIISEL:

MII/RMII Mode Configuration," on

page 37 for additional details.

Receive

Data 3

(MII Mode)

RXD3

VO8

Bit 3 of the 4 (in MII Mode) data bits that are sent

by the transceiver on the receive path.

Note:

This signal is not used in RMII Mode.

PHY Address

Configuration

Strap

PHYAD2

VIS

(PD)

Combined with PHYAD0 and PHYAD1, this

configuration strap sets the transceiver’s SMI

address.

See Note 2.1 for more information on

configuration straps.

Note:

Refer to Section 3.7.1, "PHYAD[2:0]:

PHY Address Configuration," on

page 36 for additional information.

Table 2.1 MII/RMII Signals (continued)

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

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