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A32100DX датащи(PDF) 26 Page - Actel Corporation

номер детали A32100DX
подробное описание детали  HiRel FPGAs
PDF  98 Pages
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производитель  ACTEL [Actel Corporation]
домашняя страница  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX датащи(HTML) 26 Page - Actel Corporation

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26
AC T 1 T i m i ng C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Global Clock Network
tCKH
Input Low to High
FO = 16
FO = 128
7.8
8.9
9.2
10.5
ns
tCKL
Input High to Low
FO = 16
FO = 128
10.3
11.2
12.1
13.2
ns
tPWH
Minimum Pulse Width High
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
tPWL
Minimum Pulse Width Low
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
1.9
2.9
2.2
3.4
ns
tP
Minimum Period
FO = 16
FO = 128
21.7
23.2
25.6
27.3
ns
fMAX
Maximum Frequency
FO = 16
FO = 128
46
44
40
37
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
12.1
14.2
ns
tDHL
Data to Pad Low
13.8
16.3
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.09
0.11
ns/pF
dTHL
Delta High to Low
0.12
0.15
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
15.1
17.7
ns
tDHL
Data to Pad Low
11.5
13.6
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.16
0.18
ns/pF
dTHL
Delta High to Low
0.09
0.11
ns/pF
Notes:
1.
Delays based on 50 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.



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