MGC3130 datasheet(13/40 Pages) MICROCHIP

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 2012 Microchip Technology Inc.

Advance Information

DS41667A-page 13

MGC3130

4.1

Reset Block

The Reset block combines all Reset sources. It

controls the device system’s Reset signal (SYSRST).

The following is a list of device Reset sources:

•MCLR: Master Clear Reset pin

• SWR: Software Reset available through GestIC

Library

• WDTR: Watchdog Timer Reset

A simplified block diagram of the Reset block is

illustrated in Figure 4-2.

FIGURE 4-2:

SYSTEM RESET BLOCK

DIAGRAM

4.2

Power Control and Clocks

4.2.1

POWER MANAGEMENT UNIT (PMU)

The device requires a 3.3 to 3.6V supply voltage at

VDD. Enabling the internal STEP-UP converter extends

the voltage range to 2.5 to 3.6V.

According to Figure 4-3, the used power domains are

as follows:

• VDD Domain: This domain is powered by

VDD = 2.5V to 3.6V (typical VDD = 3.3V). VDD is

the external power supply for EIO, wake-up logic,

WDTR,

internal

regulators

and

STEP-UP

converter. It is provided externally through the

VDD pin.

• VDDC Domain: This domain is powered by

VDDC = 1.8V. It is generated by an embedded low-

impedance and fast linear voltage regulator. The

voltage regulator is working under all conditions

(also during Deep Sleep mode) preserving the

MGC3130 data context. VDDC is the internal

power supply voltage for digital blocks, Reset

block and RC oscillators. An external block

capacitor, CEFCD, is required on VCAPD pin.

• VDDA Domain: This domain is powered by

VDDA = 3.0V. It is generated by an embedded low-

impedance and fast linear voltage regulator.

During Deep Sleep mode, the analog voltage

regulator is switched off. VDDA is the internal

analog power supply voltage for the ADCs and

the signal conditioning. An external block

capacitor, CEFCA, is required on VCAPA pin.

• VDDM Domain: This domain is powered by

VDDM = 3.3V. VDDM is the internal power supply

voltage for the internal Flash memory. This power

supply is depending on VDD voltage range. If

VDD ≥ 3.3V, the memory is directly powered

through the VDD pin. In case of VDD < 3.3V, the

Flash power supply is generated internally by an

embedded STEP-UP converter.

FIGURE 4-3:

POWER SCHEME BLOCK

DIAGRAM

• STEP-UP Converter: The STEP-UP converter is

generating 3.3V from the connected supply

voltage VDD (if it is lower than 3.3V). This voltage

is required by the internal Flash memory. The

required voltage reference is taken from the

voltage reference block. During Deep Sleep

mode, the converter is switched off. It requires an

external connected inductor, a filtering capacitor

and a Schottky-diode connected to the VINDS and

VCAPS pins. If the supply voltage is high enough,

the STEP-UP converter will be disabled. Please

refer to Section 9.0 “Electrical Specifications”

for more details.

MCLR

Glitch Filter

Deep sleep

WDTR

Software Reset (SWR)

WDT Time-out

SYSRST

SPU

Digital

Peripherals

Reset Block

Internal Osc.

VDDC Domain

Analog voltage

regulator

Digital voltage

regulator

Flash

Memory

Wake-up logic

WDTR

EIO

VDDM Domain

STEP-UP converter

VCAPS

VSS2

VDD

VSS1

VCAPA

VSS3

ADC

Signal Conditioning Blocks

VDDA Domain

VCAPD

VINDS

VDD Domain

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