ENC28J60_12 datasheet(97/102 Pages) MICROCHIP

97 / 102 page

 2006-2012 Microchip Technology Inc.

DS39662E-page 97

ENC28J60

INDEX

AC Characteristics

CLKOUT Pin ............................................................... 81

Industrial and Commercial .......................................... 81

Reset........................................................................... 81

SPI Interface (table) .................................................... 82

BIST

Address Fill Mode ....................................................... 76

Associated Registers .................................................. 77

EBSTCS registers....................................................... 76

EBSTSD Register ....................................................... 76

Pattern Shift Fill Mode................................................. 76

Random Data Fill Mode .............................................. 76

Usage.......................................................................... 76

Block Diagrams

Crystal Oscillator Operation .......................................... 5

ENC28J60 Architecture ................................................ 3

Ethernet Buffer Organization ...................................... 18

Ethernet Packet Format .............................................. 31

Ethernet Termination and External Connections .......... 7

External Clock Source .................................................. 5

I/O Level Shifting Using 3-State Buffers ....................... 8

I/O Level Shifting Using AND Gates ............................. 8

Interrupt Logic ............................................................. 63

LEDB Polarity and Reset Configuration........................ 8

Magic Packet Format .................................................. 52

Memory Organization.................................................. 11

On-Chip Reset Circuit ................................................. 59

Pattern Match Filter Format ........................................ 51

Typical ENC28J60 Based Interface .............................. 4

Built-in Self-Test Controller (BIST)...................................... 75

Checksum Calculations ...................................................... 72

CLKOUT Pin ......................................................................... 6

Control Register Summary............................................ 13–14

Control Registers ................................................................ 12

Map ............................................................................. 12

Customer Change Notification Service ............................... 95

Customer Notification Service............................................. 95

Customer Support............................................................... 95

DC Characteristics

Industrial and Commercial .......................................... 80

DMA Controller ................................................................... 71

Associated Registers .................................................. 72

Checksum Calculations .............................................. 72

Copying Memory......................................................... 71

Duplex Mode

Configuration and Negotiation .................................... 53

Electrical Characteristics..................................................... 79

Absolute Maximum Ratings ........................................ 79

Oscillator Timing ......................................................... 81

Requirements for External Magnetics......................... 81

EREVID Register ................................................................ 22

Errata .................................................................................... 2

Ethernet

Packet Format ............................................................ 31

CRC Field ........................................................... 32

Data Field ........................................................... 32

Destination Address ........................................... 32

Padding Field ..................................................... 32

Preamble/Start-of-Frame Delimiter..................... 31

Source Address.................................................. 32

Type/Length Field............................................... 32

Ethernet Buffer ................................................................... 17

DMA Controller

Access ................................................................ 17

Reading and Writing ................................................... 17

Receive....................................................................... 17

Transmit...................................................................... 17

Ethernet Module

Transmitting and Receiving Data

Receive Packet Layout....................................... 43

Transmit Packet Layout...................................... 40

Ethernet Overview .............................................................. 31

Flow Control........................................................................ 55

Associated Registers.................................................. 57

Full-Duplex Mode ....................................................... 55

Half-Duplex Mode....................................................... 55

Sample Full-Duplex Network (Diagram) ..................... 55

Flowcharts

Receive Filters Using AND Logic ............................... 50

Receive Filters Using OR Logic.................................. 49

Full-Duplex Mode

Operation.................................................................... 53

Half-Duplex Mode

Operation.................................................................... 53

I/O Level Shifting .................................................................. 8

Initialization......................................................................... 33

MAC Settings.............................................................. 34

PHY Settings .............................................................. 37

Receive Buffer ............................................................ 33

Receive Filters............................................................ 33

Transmit Buffer ........................................................... 33

Waiting for OST .......................................................... 33

Internet Address ................................................................. 95

Interrupts ............................................................................ 63

DMA Flag (DMAIF) ..................................................... 69

INT Enable (INTIE) ..................................................... 64

Link Change Flag (LINKIF)......................................... 69

Receive Error Flag (RXERIF) ..................................... 68

Receive Packet Pending Flag (PKTIF)....................... 69

Transmit Error Flag (TXERIF) .................................... 68

Transmit Interrupt Flag (TXIF) .................................... 68

LED Configuration ................................................................ 8

Magnetics and External Components................................... 7

Memory Organization ......................................................... 11

Microchip Internet Web Site................................................ 95

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