REV.

ADF4001

–14–

COHERENT CLOCK GENERATION

When testing A/D converters, it is often advantageous to use a

coherent test system, that is, a system that ensures a specific

relationship between the A/D converter input signal and the

A/D converter sample rate. Thus, when doing an FFT on this

data, there is no longer any need to apply the window weighting

function. Figure 8 shows how the ADF4001 can be used to handle

all the possible combinations of the input signal frequency and

sampling rate. The first ADF4001 is phase locked to a VCO. The

output of the VCO is also fed into the N divider of the second

ADF4001. This results in both ADF4001s being coherent with

f

S

= (f

IN

N1)/(R1

N2)

A/D

CONVERTER

UNDER

TEST

ADF4001

ADF4001

SINE

OUTPUT

BRUEL &

KJAER

MODEL 1051

SQUARE

OUTPUT

VCO

100MHz

LOOP

FILTER

MUXOUT

NC7S04

N2

N1

R1

SAMPLING

CLOCK

Figure 8. Coherent Clock Generator

TRI-BAND CLOCK GENERATION CIRCUIT

In multiband applications, it is necessary to realize different

clocks from one master clock frequency. For example, GSM

uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and

CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to

use the ADF4001 to generate GSM, WCDMA, and CDMA

system clocks from a single 52 MHz master clock. The low RF

low as

clock frequencies can be realized using the formula

f

REF

N

R

OUT

IN

=×

÷

()

SHUTDOWN CIRCUIT

The circuit in Figure 10 shows how to shut down both the

ADF4001 and the accompanying VCO. The ADG702 switch

goes open circuit when a Logic 1 is applied to the IN input.

The low cost switch is available in both SOT-23 and micro

SOIC packages.

19.44MHz SYSTEM

CLOCK FOR WCDMA

19.2MHz SYSTEM

CLOCK FOR CDMA

13MHz SYSTEM

CLOCK FOR GSM

R2

1300

ADF4001

65

R3

ADF4001

R1

4

ADF4001

52MHz

MASTER

CLOCK

N2

486

LOOP

FILTER

VCXO

19.44MHz

N1

1

N3

24

VCXO

13MHz

VCXO

19.2MHz

LOOP

FILTER

LOOP

FILTER

Figure 9. Tri-Band System Clock Generation

AGND

4

DGND

9

CPGND

3

ADF4001

100pF

100pF

51

7

15

16

CE

10

1

2

CP

POWER-DOWN CONTROL

DECOUPLING CAPACITORS AND INTERFACE

SIGNALS HAVE BEEN OMITTED FROM THE

DIAGRAM IN THE INTEREST OF GREATER CLARITY.

6

5

10k

LOOP

FILTER

100pF

18

18

18

100pF

ADG702

S

D

GND

IN

GND

VCO

OR

VCXO

Figure 10. Local Oscillator Shutdown Circuit

B